1. Field of the Invention
The present invention relates to a semiconductor device that achieves a reduction in a leakage current to a substrate of a vertical PNP transistor that is used as a power semiconductor element.
2. Description of the Related Art
As an example of a conventional semiconductor device, the following vertical PNP transistor is known. FIG. 8 is a cross-sectional view for describing the conventional vertical PNP transistor.
As shown in FIG. 8, an N type epitaxial layer 112 is formed on a P type silicon substrate 111. In the silicon substrate 111 and the epitaxial layer 112, an N type buried diffusion layer (hereinafter, referred to as a buried layer) 113 and a P type buried layer 114 are formed in an overlapping manner. Moreover, in the epitaxial layer 112, P type diffusion layers 115, 116 as collector regions and an N type diffusion layer 117 as a base region are formed. The P type diffusion layers 115, 116 are connected to the P type buried layer 114. Furthermore, in the N type diffusion layer 117, a P type diffusion layer 118 as an emitter region and an N type diffusion layer 119 as a base lead region are formed.
Then, an oxide film 120 is formed on the epitaxial layer 112. In the oxide film 120, contact holes 121, 122, 123, 124 and 125 are formed. Through the contact holes 121 to 125, an electrode 126, collector electrodes 127, 128, an emitter electrode 129 and a base electrode 130 are formed. This technology is described, for instance, in Japanese Patent Application Publication No. 2004-207702 (pp. 6-7 and FIG. 2).
Described will be a problem that occurs when the vertical PNP transistor shown in FIG. 8 is used in a saturation region. For example, a power supply voltage (13.0 V) is applied to the emitter electrode 129; a voltage which is substantially the same as the power supply voltage (the voltage (12.9 V) having a 0.3 V or less potential difference from the power supply voltage) is applied to the collector electrodes 127, 128; and a desired voltage is applied to the base electrode 130. Note that the power supply voltage (13.0 V) is applied to the electrode 126 connected to the epitaxial layer 112 that is positioned on the outer sides of the P type diffusion layers 115, 116.
Firstly, when the base electrode 130 is applied with 12.3 V, a forward voltage is applied between the emitter and base regions. Accordingly, the vertical PNP transistor is turned on. Then, the voltage applied to the base electrode 130 is decreased (to 12.1 V) and the base current is increased. As a result, a parasitic NPN transistor Tr11 (hereinafter, referred to as a parasite Tr11), constituted of the N type buried layer 113, the P type buried layer 114 and the N type diffusion layer 117 is turned on. At this point, in the parasite Tr11, the P type buried layer 114 serving as a base region is applied with 12.9 V, the N type diffusion layer 117 as an emitter region is applied with 12.1 V, and the N type buried layer 113 as a collector region is applied with 13.0 V.
Meanwhile, a voltage substantially the same as that applied to the parasite Tr11 is also applied to a parasitic NPN transistor Tr12 (hereinafter, referred to as a parasite Tr12) that is constituted of N type diffusion layers 131, 132 (including the epitaxial layer 112 positioned outside the P type diffusion layer 115), the P type diffusion layer 115 and the N type diffusion layer 117. Nevertheless, the parasite Tr12 has two factors to inhibit the transistor operation. The first factor is as follows. The P type diffusion layers 118 disposed around the N type diffusion layer 119 increases the parasitic resistance at an emitter region of the parasite Tr12. Thereby, a voltage applied to a PN junction region between the emitter region and a base region is decreased. The second factor is as follows. The P type diffusion layer 115 is used as the collector region of the vertical PNP transistor, and accordingly its impurity concentration is high. Thereby, it is highly likely that electrons injected from the N type diffusion layer 117 serving as the emitter region of the parasite Tr12 are recombined with positive holes in the P type diffusion layer 115 as a base region. Due to these factors, the parasite Tr11 is turned on preferentially over the parasite Tr12.
After the parasite Tr11 is turned on, potential drop occurs at the N type buried layer 113 (the potential drops from 13.0 V to 11.5 V), thereby turning on a parasite PNP transistor Tr13 (hereinafter, referred to as a parasite Tr13) that is constituted of the P type semiconductor substrate 111, the N type buried layer 113 and the P type buried layer 114. At this point, the N type buried layer 113 as a base region is applied with 11.5 V, the P type buried layer 114 as an emitter region is applied with 12.9 V, and the P type semiconductor substrate 111 as a collector region is applied with 0 V. As a result, the parasite Tr13 is continuously turned on.
To put it another way, by using the vertical PNP transistor in a saturation region, a current leaks from the power source line to the ground line, thus changing the potential of the semiconductor substrate 111, which has been set to be the ground potential. Thus, a malfunction may occur due to a latchup in a peripheral circuit formed on the same semiconductor substrate 111. As a result, due to the leakage current, it is difficult to use a vertical PNP transistor having a structure as shown in FIG. 8 in a high output circuit.